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Chapter 10 Reset and Boot
The MC_SRSL[LOC] bit is set to indicate the error.
10.2.2.6 Software reset (SW)
The SYSRESETREQ bit in the NVIC application interrupt and reset control register can
be set to force a software reset on the device. (See ARM's NVIC documentation for the
full description of the register fields, especially the VECTKEY field requirements.)
Setting SYSRESETREQ generates a software reset request. This reset forces a system
reset of all major components except for the debug module. A software reset causes
SRSH[SW] bit to set.
10.2.2.7 Lockup reset (LOCKUP)
The LOCKUP gives immediate indication of seriously errant kernel software. This is the
result of the core being locked because of an unrecoverable exception following the
activation of the processor's built in system state protection hardware.
The LOCKUP condition causes a system reset and also causes SRSH[LOCKUP] bit to
set.
10.2.2.8 MDM-AP system reset request
Set the system reset request bit in the MDM-AP control register to initiate a system reset.
This is the primary method for resets via the JTAG interface. The system reset is held
until this bit is cleared.
Set the core hold reset bit in the MDM-AP control register to hold the core in reset as the
rest of the chip comes out of system reset.
10.2.3 Debug resets
The following sections detail the debug resets available on the device.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
133
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