Tap Controller State Machine - NXP Semiconductors freescale KV4 Series Reference Manual

Chapter 48 JTAG Controller (JTAGC)
Data is shifted between TDI and TDO though the selected register starting with the least
significant bit, as illustrated in the following figure. This applies for the instruction
register, test data registers, and the bypass register.
MSB LSB
TDI Selected Register
TDO
Figure 48-3. Shifting data through a register

48.4.3 TAP controller state machine

The TAP controller is a synchronous state machine that interprets the sequence of logical
values on the TMS pin. The following figure shows the machine's states. The value
shown next to each state is the value of the TMS signal sampled on the rising edge of the
TCK signal. As the following figure shows, holding TMS at logic 1 while clocking TCK
through a sufficient number of rising edges also causes the state machine to enter the
Test-Logic-Reset state.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc. 1343