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Functional Description
37.5.3.1 Load Enable
MCTRL[LDOK] enables loading of the following PWM generator parameters:
• The prescaler divisor—from CTRL[PRSC]
• The PWM period and pulse width—from the INIT and VALx registers
MCTRL[LDOK] allows software to finish calculating all of these PWM parameters so
they can be synchronously updated. The CTRL[PRSC], INIT, and VALx registers are
loaded by software into a set of outer buffers. When MCTRL[LDOK] is set, these values
are transferred to an inner set of registers at the beginning of the next PWM reload cycle
to be used by the PWM generator. These values can be transfered to the inner set of
registers immediately upon setting MCTRL[LDOK] if CTRL[LDMOD] is set. Set
MCTRL[LDOK] by reading it when it is a logic zero and then writing a logic one to it.
After loading, MCTRL[LDOK] is automatically cleared.
37.5.3.2 Load Frequency
CTRL[LDFQ] selects an integral loading frequency of one to 16 PWM reload
opportunities. CTRL[LDFQ] takes effect at every PWM reload opportunity, regardless
the state of MCTRL[LDOK]. CTRL[HALF] and CTRL[FULL] control reload timing. If
CTRL[FULL] is set, a reload opportunity occurs at the end of every PWM cycle when
the count equals VAL1. If CTRL[HALF] is set, a reload opportunity occurs at the half
cycle when the count equals VAL0. If both CTRL[HALF] and CTRL[FULL] are set, a
reload opportunity occurs twice per PWM cycle when the count equals VAL1 and when
it equals VAL0.
Counter
Reload
Change
Reload
Frequency
Figure 37-251. Full Cycle Reload Frequency Change
856
Every two
to every four
opportunities
opportunities
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
to every
opportunity
Freescale Semiconductor, Inc.
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