Table of Contents
Advertisement
SPI module changes
• In
Memory map/register
• In
Message buffer
structure, added the note "When configuring CAN FD frames, the RTR bit must be negated."
• Revised
CAN FD
frames.
• Revised
Transceiver Delay
• In
Rx FIFO
structure, modified explanation of additional memory area to account for case where there is a maximum of
sixteen message buffers.
• In
Table
43-2, removed rows for IMASK2 and IFLAG2 registers.
A.43 SPI module changes
• Included two topics
Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
1, CPHA =
1).
• Reduced bit width of SPI_CTARn_SLAVE [FMSZ] from 5 to 4.
• In RSER register, added "Always write the reset value to this field." to some of the Reserved bits. Also, updated bit
field access to RW for these bits.
• In PUSHR register, added note "Always write the reset value to this field." to Reserved bits. Also, updated bit field
access to RW for these bits.
• In
Memory Map/Register Definition
• Updated bit field description for SPI_MCR[PCSIS].
• Updated bit field description for SPI_PUSHR[PCS].
•
Continuous Serial Communications Clock
SCK only if MCR[HALT] bit is low'.
• Editorial updates.
• In "SPI memory map" table of
"See section" to actual value.
A.44 I2C changes
• Added the handling of START/STOP interrupt in the ISR flowchart
A.45 UART changes
• No substantial content changes
A.46 GPIO changes
• Updated
Features
1356
definition, deleted the "FlexCAN Memory Partition for CAN FD" section.
Compensation.
section, added RXFRn to statement re. write accesses results in transfer error.
section updated with sentence, 'Enabling this bit generates the Continuous
Memory Map/Register Definition
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
and
Modified SPI Transfer Format (MTFE =
section, changed reset value of Status Register from
Typical I2C interrupt
routine.
Freescale Semiconductor, Inc.
Advertisement
Table of Contents
