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AIPS module changes
• In
Memory Map / Register Definition
• In
General operation
:
• Changed "When a slave bus is being idled by the crossbar,..." to "When a slave bus, other than the flash (if
present), is being idled by the crossbar,...".
• Added paragraph that begins, "If present, the flash slave port parks..."
A.20 AIPS module changes
• No substantial content changes
A.21 DMAMUX module changes
• Updated the base address of the registers
A.22 eDMA module changes
• No substantial content changes
• Removed "(4 beats of 64 bits)" from TCDn_ATTR[SSIZE] bit field description for b101 value.
•
Fault reporting and handling
•
Block parts
: Changed "16/32 bytes of register storage" to "a data buffer" in Data path description.
• Added note to DMA_CR[CLM] description re. restriction on use of continuous link mode.
• In section "Peak transfer rates", added a note stating "All architectures will not meet the assumptions listed above. See
the SRAM configuration section for more information."
•
Features
: Removed bullet "Error detection and error correction".
•
Features
: Removed bullet beginning with, "Support to cancel transfers..."
•
Memory map/register definition
• Made editorial changes in
• Editorial changes.
A.23 EWM changes
• No substantial content changes
A.24 WDOG changes
• No substantial content changes
1352
added paragraph stating to see chip-specific information re. arbitration.
: Added note re. cancel transfer request. Added note re. channel priority errors.
: Edited image in TCD structure for clarity for word at 0008h.
Fault reporting and
handling.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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