Buses, Interconnects, And Interfaces; System Tick Timer; Debug Facilities - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

ARM Cortex-M4 Core Configuration

Table 3-1. Reference links to related information (continued)

Private Peripheral Bus

Miscellaneous Control

(PPB) module

Private Peripheral Bus

Single-precision floating

(PPB) module

3.1.1 Buses, interconnects, and interfaces

The ARM Cortex-M4 core has four buses as described in the following table.

Table 3-2. Buses of ARM Cortex-M4 core and their description

Instruction code (ICODE) bus The ICODE and DCODE buses are muxed. This muxed bus is called the CODE bus and is

Data code (DCODE) bus

Private peripheral (PPB) bus

The System Tick Timer's clock source is always the core clock, FCLK. This results in the

• The CLKSOURCE bit in SysTick Control and Status register is always set to select

the core clock.

• Because the timing reference (FCLK) is a variable frequency, the TENMS bit in the

SysTick Calibration Value Register is always zero.

• The NOREF bit in SysTick Calibration Value Register is always set, implying that

FCLK is the only available source of reference timing.

This device has extensive debug capabilities including run control and tracing

capabilities. The standard ARM debug port that supports JTAG and SWD interfaces.

Also the cJTAG interface is supported on this device.

Related module

Module (MCM)

point unit (FPU)

connected to the crossbar switch via a single master port. In addition, the CODE bus is also

tightly coupled to the lower half of the system RAM (SRAM_L).

The system bus is connected to a separate master port on the crossbar. In addition, the

system bus is tightly coupled to the upper half system RAM (SRAM_U).

The PPB provides access to these modules:

• ARM modules such as the NVIC, ITM, DWT, FBP, and ROM table

• Freescale Miscellaneous Control Module (MCM)

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.