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Application information
46.9.1 Transmit/receive data buffer operation
The UART has independent receive and transmit buffers. The size of these buffers may
vary depending on the implementation of the module. The implemented size of the
buffers is a fixed constant via PFIFO[TXFIFOSIZE] and PFIFO[RXFIFOSIZE].
Additionally, legacy support is provided that allows for the FIFO structure to operate as a
depth of one. This is the default/reset behavior of the module and can be adjusted using
the PFIFO[RXFE] and PFIFO[TXFE] bits. Individual watermark levels are also provided
for transmit and receive.
There are multiple ways to ensure that a data block, which is a set of characters, has
completed transmission. These methods include:
1. Set TXFIFO[TXWATER] to 0. TDRE asserts when there is no further data in the
transmit buffer. Alternatively the S1[TC] flag can be used to indicate when the
transmit shift register is also empty.
2. Poll TCFIFO[TXCOUNT]. Assuming that only data for a data block has been put
into the data buffer, when TCFIFO[TXCOUNT] = 0, all data has been transmitted or
is in the process of transmission.
3. S1[TC] can be monitored. When S1[TC] asserts, it indicates that all data has been
transmitted and there is no data currently being transmitted in the shift register.
46.9.2 Initialization sequence
To initiate a UART transmission:
1. Configure the UART.
a. Select a baud rate. Write this value to the UART baud registers (BDH/L) to
begin the baud rate generator. Remember that the baud rate generator is disabled
when the baud rate is zero. Writing to the BDH has no effect without also
writing to BDL.
b. Write to C1 to configure word length, parity, and other configuration bits
(LOOPS, RSRC, M, WAKE, ILT, PE, and PT). Write to C4, MA1, and MA2 to
configure.
c. Enable the transmitter, interrupts, receiver, and wakeup as required, by writing to
C2 (TIE, TCIE, RIE, ILIE, TE, RE, RWU, and SBK), S2 (MSBF and BRK13),
and C3 (ORIE, NEIE, PEIE, and FEIE). A preamble or idle character is then
shifted out of the transmitter shift register.
1322
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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