Table of Contents
Advertisement
25.6 Backup reset generator
The backup reset generator generates the final reset which goes out to the system. It has a
backup mechanism which ensures that in case the bus clock stops and prevents the main
state machine from generating a reset exception/interrupt, the watchdog timer's time-out
is separately routed out as a reset to the system. Two successive timer time-outs without
an intervening system reset result in the backup reset generator routing out the time-out
signal as a reset to the system.
25.7 Generated resets and interrupts
The watchdog generates a reset in the following events, also referred to as exceptions:
• A watchdog time-out
• Failure to unlock the watchdog within WCT time after system reset deassertion
• No update of the control and configuration registers within the WCT window after
unlocking. At least one of the following registers must be written to within the WCT
window to avoid reset:
• WDOG_ST_CTRL_H, WDOG_ST_CTRL_L
• WDOG_TO_VAL_H, WDOG_TO_VAL_L
• WDOG_WIN_H, WDOG_WIN_L
• WDOG_PRESCALER
• A value other than the unlock sequence or the refresh sequence is written to the
unlock and/or refresh registers, respectively.
• A gap of more than 20 bus cycles exists between the writes of two values of the
unlock sequence.
• A gap of more than 20 bus cycles exists between the writes of two values of the
refresh sequence.
The watchdog can also generate an interrupt. If IRQ_RST_EN is set, then on the above
mentioned events WDOG_ST_CTRL_L[INT_FLG] is set, generating an interrupt. A
watchdog reset is also generated WCT time later to ensure the watchdog is fault tolerant.
The interrupt can be cleared by writing 1 to INT_FLG.
Freescale Semiconductor, Inc.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 25 Watchdog Timer (WDOG)
471
Advertisement
Table of Contents
