Fault Reporting And Handling - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
eDMA
eDMA En g in e
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Data Path
Write Data
Address

23.4.2 Fault reporting and handling

Channel errors are reported in the Error Status register (DMAx_ES) and can be caused
by:
• A configuration error, which is an illegal setting in the transfer-control descriptor or
an illegal priority register setting in Fixed-Arbitration mode, or
• An error termination to a bus master read or write cycle
A configuration error is reported when the starting source or destination address, source
or destination offsets, minor loop byte count, or the transfer size represent an inconsistent
state. Each of these possible causes are detailed below:
• The addresses and offsets must be aligned on 0-modulo-transfer-size boundaries.
• The minor loop byte count must be a multiple of the source and destination transfer
sizes.
428
Address Path
Figure 23-292. eDMA operation, part 3
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Transfer
Control
Descriptor (TCD)
64
Program Model/
Channel Arbitration
Control
eDMA Peripheral
eDMA Done
Request
Freescale Semiconductor, Inc.
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Write Data
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1
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