End Of Queue Interrupt Request; Transmit Fifo Fill Interrupt Or Dma Request - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

Table 44-44. Interrupt and DMA request conditions (continued)

RX FIFO Drain

RX FIFO Overflow

Each condition has a flag bit in the module Status Register (SR) and a Request Enable bit

in the DMA/Interrupt Request Select and Enable Register (RSER). Certain flags (as

shown in above table) generate interrupt requests or DMA requests depending on

configuration of RSER register.

The module also provides a global interrupt request line, which is asserted when any of

individual interrupt requests lines is asserted.

44.5.7.1 End Of Queue interrupt request

The End Of Queue (EOQ) interrupt request indicates that the end of a transmit queue is

reached. The module generates the interrupt request when EOQ interrupt requests are

enabled (RSER[EOQF_RE]) and the EOQ bit in the executing SPI command is 1.

The module generates the interrupt request when the last bit of the SPI frame with EOQ

bit set is transmitted.

The Transmit FIFO Fill Request indicates that the TX FIFO is not full. The Transmit

FIFO Fill Request is generated when the number of entries in the TX FIFO is less than

the maximum number of possible entries, and the TFFF_RE bit in the RSER is set. The

TFFF_DIRS bit in the RSER selects whether a DMA request or an interrupt request is

TFFF flag clears automatically when DMA is used to fill TX

To clear TFFF when not using DMA, follow these steps for

every PUSH performed using CPU to fill TX FIFO:

1. Wait until TFFF = 1.

2. Write data to PUSHR using CPU.

3. Clear TFFF by writing a 1 to its location. If TX FIFO is not

full, this flag will not clear.

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.