Normal Mode Operation - NXP Semiconductors freescale KV4 Series Reference Manual

Functional Description
34.5.2 ADC Sample Conversion Operating Modes
The ADC consists of a cyclic, algorithmic architecture using two recursive sub-ranging
sections (RSD 1 and RSD 2) as shown in the following figure. Each sub-ranging section
resolves a single bit for each conversion clock, resulting in an overall conversion rate of 2
bits per clock cycle. Each sub-ranging section runs at a maximum clock speed of 25
MHz, so a complete 12-bit conversion can be accommodated in 240 ns, not including
sample or post-processing time.
ANA0
Analog
Input Select
Multiplex
ANA7
ANB0
Analog
Input Select
Multiplex
ANB1

34.5.2.1 Normal Mode Operation

The ADC has two normal operating modes: single-ended mode and differential mode.
For a given sample, the mode of operation is determined by the CTRL1[CHNCFG] field:
710
Interface Function/
Program Gain
Interface Function/
Program Gain
Figure 34-97. Top-Level Diagram of Cyclic ADC
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Multiplex
RSD 1
θ θ
θ 1
Cyclic ADC Core
Converter A
Multiplex
RSD 1
θ 1
Cyclic ADC Core
Converter B
RSD 2
θ 2 2
RSD 2
θ 2 2
Freescale Semiconductor, Inc.