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Introduction
44.2.1 Block Diagram
The block diagram of this module is as follows:
eDMA
DMA and Interrupt Control
PUSHR
Data
CMD
SPI
Baud Rate, Delay &
Transfer Control
44.2.2 Features
The module supports the following features:
• Full-duplex, three-wire synchronous transfers
• Master mode
• Slave mode
• Data streaming operation in Slave mode with continuous slave selection
• Buffered transmit operation using the transmit first in first out (TX FIFO) with depth
of 4 entries
1172
INTC
SPI
POPR
Data
32
16
Shift Register
Figure 44-1. SPI Block Diagram
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Peripheral Bus
Clock/Reset
8
SOUT
SIN
SCK
PCS[x]/SS/PCSS
Freescale Semiconductor, Inc.
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