Modes Of Operation - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction
• Interrupt-driven byte-by-byte data transfer
• Arbitration-lost interrupt with automatic mode switching from master to slave
• Calling address identification interrupt
• START and STOP signal generation and detection
• Repeated START signal generation and detection
• Acknowledge bit generation and detection
• Bus busy detection
• General call recognition
• 10-bit address extension
• Support for System Management Bus (SMBus) Specification, version 2
• Programmable input glitch filter
• Low power mode wakeup on slave address match
• Range slave address support
• DMA support

45.2.2 Modes of operation

The I2C module's operation in various low power modes is as follows:
• Run mode: This is the basic mode of operation. To conserve power in this mode,
disable the module.
• Wait mode: The module continues to operate when the core is in Wait mode and can
provide a wakeup interrupt.
• Stop mode: The module is inactive in Stop mode for reduced power consumption,
except that address matching is enabled in Stop mode. The STOP instruction does
not affect the I2C module's register states.
45.2.3 Block diagram
The following figure is a functional block diagram of the I2C module.
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.