Nine-Bit Format With Parity Enabled; Non-Memory Mapped Tenth Bit For Parity; Single-Wire Operation - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description

46.5.4.3.4 Nine-bit format with parity enabled

START
BIT 0
BIT
Figure 46-83. Eight bits of data with LSB first and parity
START
BIT 7
BIT
Figure 46-84. Eight bits of data with MSB first and parity

46.5.4.3.5 Non-memory mapped tenth bit for parity

The most significant memory-mapped bit can be used for address mark wakeup.
START
BIT 0
BIT
Figure 46-85. Nine bits of data with LSB first and parity
ADDRESS
MARK
START
BIT 8
BIT
Figure 46-86. Nine bits of data with MSB first and parity

46.5.5 Single-wire operation

Normally, the UART uses two pins for transmitting and receiving. In single wire
operation, the RXD pin is disconnected from the UART and the UART implements a
half-duplex serial connection. The UART uses the TXD pin for both receiving and
transmitting.
Figure 46-87. Single-wire operation (C1[LOOPS] = 1, C1[RSRC] = 1)
1318
BIT 1 BIT 2 BIT 3 BIT 4
BIT 6 BIT 5 BIT 4 BIT 3
BIT 1 BIT 2 BIT 3 BIT 4 BIT 5
BIT 7 BIT 6 BIT 5 BIT 4 BIT 3
TXINV
TRANSMITTER
RECEIVER
RXINV
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
BIT 7 PARITY STOP
BIT 5 BIT 6
BIT 0 PARITY STOP
BIT 2 BIT 1
ADDRESS
MARK
BIT 8 PARITY STOP
BIT 6 BIT 7
BIT 0 PARITY STOP
BIT 2 BIT 1
Tx pin output
Tx pin input
RXD
START
BIT
BIT
START
BIT
BIT
START
BIT
BIT
START
BIT
BIT
Freescale Semiconductor, Inc.