Low Power Modes - NXP Semiconductors freescale KV4 Series Reference Manual

• Triggered scan. Identical to the corresponding once scan modes except that resetting
CTRL*[SYNC*] bits is not necessary.
• Looping scan. Automatically restarts a scan, either parallel or sequential, as soon as
the previous scan completes. In parallel looping scan modes, the A converter scan
restarts as soon as the A converter scan completes and the B converter scan restarts
as soon as the B converter scan completes. All subsequent start and sync pulses are
ignored after the scan begins unless the scan is paused by the SCTRL[SC] bits.
Scanning can only be terminated by setting the STOP bit.
All scan modes ignore sync pulses while a scan is in process unless the scan is paused by
the SCTRL[SC] bits. Once scan modes continue to ignore sync pulses even after the scan
completes until the CTRL*[SYNC*] bit is set again. However, a reset can occur any time
including during the scan. The SYNC0 input is re-armed by setting the CTRL1[SYNC0]
bit, and the SYNC1 input is reset by setting the CTRL2[SYNC1] bit. A reset can be
performed any time after a scan starts.
34.5.6 Power Management
The five supported power modes are discussed in order from highest to lowest power
usage at the expense of increased conversion latency and/or startup delay. See the Clocks
section for details on the various clocks referenced here.

34.5.6.1 Low Power Modes

In the following table, ADC's low-power modes are discussed in order from from highest
to lowest power usage.
Mode
Normal power At least one ADC converter is powered up (PWR[PD0 or PD1] is 0), the PWR[APD and ASB] bits
are both 0, and the SIM_SCGC5[ADC] bit is 1. The ADC uses the conversion clock as the ADC
clock source in either active or idle. The conversion clock should be configured at or near 25 MHz
to minimize conversion latency although PWR2[SPEEDn] can be used for reduced power
consumption when lower conversion frequencies are acceptable . No startup delay
(PWR[PUDELAY]) is imposed.
Auto-standby At least one ADC converter is powered up (PWR[PD0 or PD1] is 0), PWR[APD] is 0, PWR[ASB] is
1 and MCGIRC enabled. The ADC uses the conversion clock when active and MCGIRC when
idle. The standby (low current) state automatically engages when the ADC is idle. The conversion
clock should be configured at or near 25 MHz to minimize conversion latency when active
although PWR2[SPEEDn] can be used for reduced power consumption when lower conversion
frequencies are acceptable. At the start of all scans, there is a startup delay of PWR[PUDELAY]
ADC clocks to engage the conversion clock and revert from standby to normal current mode.
Auto-standby is a compromise between normal and auto-powerdown modes. This mode offers
moderate power savings at the cost of a moderate latency when leaving the idle state to start a
new scan.
Freescale Semiconductor, Inc.
Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
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