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40.4.5 Timer Flag Register (PIT_TFLGn)
These registers hold the PIT interrupt flags.
Access: User read/write
Address: 4003_7000h base + 10Ch offset + (16d × i), where i=0d to 3d
Bit
31
30
29
R
W
Reset
0
0
0
Bit
15
14
13
R
W
Reset
0
0
0
Field
31–1
This field is reserved.
Reserved
This read-only field is reserved and always has the value 0.
0
Timer Interrupt Flag
TIF
Sets to 1 at the end of the timer period. Writing 1 to this flag clears it. Writing 0 has no effect. If enabled,
or, when TCTRLn[TIE] = 1, TIF causes an interrupt request.
0
Timeout has not yet occurred.
1
Timeout has occurred.
40.5 Functional description
This section provides the functional description of the module.
40.5.1 General operation
This section gives detailed information on the internal operation of the module. Each
timer can be used to generate trigger pulses and interrupts. Each interrupt is available on
a separate interrupt line.
Freescale Semiconductor, Inc.
28
27
26
25
0
0
0
0
12
11
10
9
0
0
0
0
PIT_TFLGn field descriptions
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 40 Periodic Interrupt Timer (PIT)
24
23
22
21
0
0
0
0
0
8
7
6
5
0
0
0
0
0
Description
20
19
18
17
0
0
0
0
4
3
2
1
TIF
w1c
0
0
0
0
16
0
0
0
1033
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