Byte Transfer Interrupt; Address Detect Interrupt - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

45.5.6 Interrupts

The I2C module generates an interrupt when any of the events in the table found here

occur, provided that the IICIE bit is set.

The interrupt is driven by the IICIF bit (of the I2C Status Register) and masked with the

IICIE bit (of the I2C Control Register 1). The IICIF bit must be cleared (by software) by

writing 1 to it in the interrupt routine. The SMBus timeouts interrupt is driven by SLTF

and masked with the IICIE bit. The SLTF bit must be cleared by software by writing 1 to

it in the interrupt routine. You can determine the interrupt type by reading the Status

In master receive mode, the FACK bit must be set to zero

before the last byte transfer.

Interrupt source

Complete 1-byte transfer

Match of received calling address

Arbitration lost

C bus stop detection

C bus start detection

SMBus SCL low timeout

SMBus SCL high SDA low timeout

Wakeup from stop or wait mode

45.5.6.1 Byte transfer interrupt

The Transfer Complete Flag (TCF) bit is set at the falling edge of the ninth clock to

indicate the completion of a byte and acknowledgement transfer. When FACK is enabled,

TCF is then set at the falling edge of eighth clock to indicate the completion of byte.

When the calling address matches the programmed slave address (I2C Address Register)

or when the GCAEN bit is set and a general call is received, the IAAS bit in the Status

check the SRW bit and set its Tx mode accordingly.

Freescale Semiconductor, Inc.

Table 45-18. Interrupt summary

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 45 Inter-Integrated Circuit (I2C)

Local enable

IICIE & SSIE

IICIE & SSIE

IICIE & SHTF2IE

IICIE & WUEN