Output Logic - NXP Semiconductors freescale KV4 Series Reference Manual

Functional Description
37.5.2.9.1 Fractional Delay Logic with Micro-Edge Placement Block
Using the micro-edge placer block requires that the IPBus clock to the PWM be set at a
defined frequency. The micro-edge placer is powered up by setting
FRCTRL[FRAC_PU]. Enable fine edge control on the various PWM edges by setting
FRCTRL[FRACx_EN]. The fractional values in the FRACVALx registers allow placing
the PWM edge or PWM period to a granularity of 1/32 of the IPBus clock period. For
example, if you desire the rising edge of the PWMA output to occur at a count of 12.25,
then program VAL2 with 0x000C and FRACVAL2 with 0x4000. Using FRACVAL1
will adjust the PWM period with the same granularity of 1/32 of a clock period.
If the FRCTRL[FRAC_PU] bits in all of the submodules are clear, then the micro-edge
placer is powered down, and alternate clock frequencies can be used without the micro-
edge placement feature.
37.5.2.9.2 Fractional Delay Logic without Micro-Edge Placement Block
For submodules that are not supported by the micro-edge placer, the PWM can use
dithering to simulate fine edge control. Enable this feature by setting the
FRCTRL[FRAC1_EN], FRCTRL[FRAC23_EN], and FRCTRL[FRAC45_EN] bits. It is
unnecessary to set FRCTRL[FRAC_PU]. The PWM period or the PWM edges will dither
from the nearest whole number values to achieve an average value that is equivalent to
the programmed fractional value. The added cycles are based on the accumulation of the
fractional component. For example, if you want the PWM period to be 50.25 clock
cycles, then program VAL1 with 0x0032 and FRACVAL1 with 0x4000. The PWM
period will be 50 cycles long most of the time, but will occasionally be 51 cycles long to
achieve a long-term average of 50.25 cycles.
In submodules that are not supported by a micro-edge placer, the clock frequency is not
required to be any specific value to achieve proper operation.

37.5.2.10 Output Logic

The following figure shows the output logic of each submodule including how each
PWM output has individual fault disabling, polarity control, and output enable. This
allows for maximum flexibility when interfacing to the external circuitry.
The PWM23 and PWM45 signals which are output from the deadtime logic (refer to the
figure) are positive true signals. In other words, a high level on these signals should result
in the corresponding transistor in the PWM inverter being turned ON. The voltage level
required at the PWM output pin to turn the transistor ON or OFF is a function of the logic
between the pin and the transistor. Therefore, it is imperative that the user program
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
848 Freescale Semiconductor, Inc.