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Memory map/register definition
23.3.3 TCD structure
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
0000h
0004h
{
SMOD
SSIZE
0008h
000Ch
0010h
CITER or
0014h
CITER.LINKCH
0018h
BITER or
001Ch
BITER.LINKCH
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9
23.3.4 Reserved memory and bit fields
• Reading reserved bits in a register returns the value of zero.
• Writes to reserved bits in a register are ignored.
• Reading or writing a reserved memory location generates a bus error.
Absolute
address
(hex)
4000_8000
Control Register (DMA_CR)
4000_8004
Error Status Register (DMA_ES)
4000_800C Enable Request Register (DMA_ERQ)
4000_8014
Enable Error Interrupt Register (DMA_EEI)
4000_8018
Clear Enable Error Interrupt Register (DMA_CEEI)
4000_8019
Set Enable Error Interrupt Register (DMA_SEEI)
372
SADDR
DMOD
DSIZE
NBYTES
MLOFF or NBYTES
SLAST
DADDR
CITER
DLAST_SGA
BITER
BWC
DMA memory map
Register name
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
8
7
6
5
4
3
2
1
0
SOFF
NBYTES
DOFF
8
7
6
5
4
3
2
1
0
Width
Access
Reset value
(in bits)
32
R/W
0000_0000h
32
R
0000_0000h
32
R/W
0000_0000h
32
R/W
0000_0000h
W
8
(always
00h
reads 0)
W
8
(always
00h
reads 0)
Freescale Semiconductor, Inc.
{
DMA_CR[EMLM] disabled
{
DMA_CR[EMLM] enabled
Section/
page
23.3.1/383
23.3.2/386
23.3.3/388
23.3.4/390
23.3.5/392
23.3.6/393
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