Fast Ack And Nack - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
CSMBCLK TIMEOUT SEXT and CSMBCLK TIMEOUT
MEXT are optional functions that are implemented in the
second step.

45.5.4.2 FAST ACK and NACK

To improve reliability and communication robustness, implementation of packet error
checking (PEC) by SMBus devices is optional for SMBus devices but required for
devices participating in and only during the address resolution protocol (ARP) process.
The PEC is a CRC-8 error checking byte, calculated on all the message bytes. The PEC is
appended to the message by the device that supplied the last data byte. If the PEC is
present but not correct, a NACK is issued by the receiver. Otherwise an ACK is issued.
To calculate the CRC-8 by software, this module can hold the SCL line low after
receiving the eighth SCL (8th bit) if this byte is a data byte. So software can determine
whether an ACK or NACK should be sent to the bus by setting or clearing the TXAK bit
if the FACK (fast ACK/NACK enable) bit is enabled.
SMBus requires a device always to acknowledge its own address, as a mechanism to
detect the presence of a removable device (such as a battery or docking station) on the
bus. In addition to indicating a slave device busy condition, SMBus uses the NACK
mechanism to indicate the reception of an invalid command or invalid data. Because such
a condition may occur on the last byte of the transfer, SMBus devices are required to
have the ability to generate the not acknowledge after the transfer of each byte and before
the completion of the transaction. This requirement is important because SMBus does not
provide any other resend signaling. This difference in the use of the NACK signaling has
implications on the specific implementation of the SMBus port, especially in devices that
handle critical system data such as the SMBus host and the SBS components.
In the last byte of master receive slave transmit mode, the
master must send a NACK to the bus, so FACK must be
switched off before the last byte transmits.
45.5.5 Resets
The I2C module is disabled after a reset. The I2C module cannot cause a core reset.
1256
NOTE
NOTE
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.