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Functional description
3. If PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=00, then VLPS mode is entered instead of STOP. If
PMCTRL[STOPM]=000 and STOPCTRL[PSTOPO]=01 or 10, then only a Partial Stop mode is entered instead of VLPS
16.4.2 Power mode entry/exit sequencing
When entering or exiting low-power modes, the system must conform to an orderly
sequence to manage transitions safely.
The SMC manages the system's entry into and exit from all power modes. This diagram
illustrates the connections of the SMC with other system components in the chip that are
necessary to sequence the system through all power modes.
16.4.2.1 Stop mode entry sequence
Entry into a low-power stop mode (Stop, VLPS, VLLSx) is initiated by a CPU executing
the WFI instruction. After the instruction is executed, the following sequence occurs:
1. The CPU clock is gated off immediately.
2. Requests are made to all non-CPU bus masters to enter Stop mode.
3. After all masters have acknowledged they are ready to enter Stop mode, requests are
made to all bus slaves to enter Stop mode.
4. After all slaves have acknowledged they are ready to enter Stop mode, all system and
bus clocks are gated off.
5. Clock generators are disabled in the MCG.
6. The on-chip regulator in the PMC and internal power switches are configured to
meet the power consumption goals for the targeted low-power mode.
16.4.2.2 Stop mode exit sequence
Exit from a low-power stop mode is initiated either by a reset or an interrupt event. The
following sequence then executes to restore the system to a run mode (RUN or VLPR):
1. The on-chip regulator in the PMC and internal power switches are restored.
2. Clock generators are enabled in the MCG.
3. System and bus clocks are enabled to all masters and slaves.
4. The CPU clock is enabled and the CPU begins servicing the reset or interrupt that
initiated the exit from the low-power stop mode.
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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