Memory Map/Register Definition; Flexcan Memory Mapping - NXP Semiconductors freescale KV4 Series Reference Manual

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Memory map/register definition

43.3.2 CAN Tx

This pin is the transmit pin to the CAN bus transceiver. Dominant state is represented by

logic level 0. Recessive state is represented by logic level 1.

43.4 Memory map/register definition

This section describes the registers and data structures in the FlexCAN module. The base

address of the module depends on the particular memory map of the MCU.

The memory map for the FlexCAN module is shown in the following table.

The address space occupied by FlexCAN has 128 bytes for registers starting at the

module base address, followed by embedded RAM starting at address 0x0080.

Each individual register is identified by its complete name and the corresponding

mnemonic. The access type can be Supervisor (S) or Unrestricted (U). Most of the

registers can be configured to have either Supervisor or Unrestricted access by

programming the SUPV field in the MCR register. These registers are identified as S/U

in the Access column of

Table 43-2. Register access and reset information

Module Configuration Register (MCR)

Control 1 register (CTRL1)

Free Running Timer register (TIMER)

Rx Mailboxes Global Mask register (RXMGMASK)

Rx Buffer 14 Mask register (RX14MASK)

Rx Buffer 15 Mask register (RX15MASK)

Error Counter Register (ECR)

Error and Status 1 Register (ESR1)

Interrupt Masks 1 register (IMASK1)

Interrupt Flags 1 register (IFLAG1)

Control 2 Register (CTRL2)

Error and Status 2 Register (ESR2)

CRC Register (CRCR)

Table continues on the next page...

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.