Timing Specifications - NXP Semiconductors freescale KV4 Series Reference Manual

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34.9 Timing Specifications

The following figure shows a timing diagram for the ADC module. The ADC is assumed

to be in Once or Triggered mode, so the ADC clock is shown in the OFF state prior to the

SYNC pulse or START bit write. The ADC clock restarts (switching high) within 1 to 2

IP bus clocks of that event. ADC_CLK is derived from the ROSC or PLL output. The

frequency relationship is programmable. Conversions are pipelined. The second start

command is ignored because the ADC is busy with the previous start request. The third

start command is recognized and is synchronized to the positive edge of the ADC clock

when the conversion process is restarted. The ADC has two possible interrupts that are

latched in the ADSTAT register:

• Conversion complete interrupt (End of Scan interrupt, EOSIx)

• Zero crossing or limit error interrupt (ZCI, LLMTI, and HLMTI)

Sync-Pulse or

Multiplex Select

(ADCSTAT Bit 15)

(If Enabled)

As the figure shows, a conversion is initiated by (1) a sync pulse originating from the

timer module or by (2) a write to a start bit. In APD or ASB mode, a delay of PWR

[PUDELAY] ADC clock cycles is imposed. The conversion is initiated in the next clock

cycle. The ADC clock period is determined by the CTRL2[DIV0] or PWR2[DIV1] value

and the fast peripheral clock.

The first conversion takes 8.5 ADC clocks to be valid. Then, each additional sample

takes only six ADC clocks. The start conversion command is latched and the real

conversion process is synchronized to the positive edge of the ADC clock.

Freescale Semiconductor, Inc.

Chapter 34 12-bit Cyclic Analog-to-Digital Converter (ADC)

Figure 34-101. ADC Timing

KV4x Reference Manual, Rev. 2, 02/2015