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46.9.6 Legacy and reverse compatibility considerations
Recent versions of the UART have added several new features. Whenever reasonably
possible, reverse compatibility was maintained. However, in some cases this was either
not feasible or the behavior was deemed as not intended. This section describes several
differences to legacy operation that resulted from these recent enhancements. If
application code from previous versions is used, it must be reviewed and modified to take
the following items into account. Depending on the application code, additional items
that are not listed here may also need to be considered.
1. Various reserved registers and register bits are used, such as, MSFB and M10.
2. This module now generates an error when invalid address spaces are used.
3. While documentation indicated otherwise, in some cases it was possible for
S1[IDLE] to assert even if S1[OR] was set.
4. S1[OR] will be set only if the data buffer (FIFO) does not have sufficient room.
Previously, the data buffer was always a fixed size of one and the S1[OR] flag would
set so long as S1[RDRF] was set even if there was room in the data buffer. While the
clearing mechanism has remained the same for S1[RDRF], keeping the OR flag
assertion tied to the RDRF event rather than the data buffer being full would have
greatly reduced the usefulness of the buffer when its size is larger than one.
5. Previously, when C2[RWU] was set (and WAKE = 0), the IDLE flag could reassert
up to every bit period causing an interrupt and requiring the host processor to reassert
C2[RWU]. This behavior has been modified. Now, when C2[RWU] is set (and
WAKE = 0), at least one non-idle bit must be detected before an idle can be detected.
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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