Timing Examples - NXP Semiconductors freescale KV4 Series Reference Manual

46.5.4.3 Timing examples

Timing examples of these configurations in the NRZ mark/space data format are
illustrated in the following figures. The timing examples show all of the configurations in
the following sub-sections along with the LSB and MSB first variations. This section
explains the data formats available assuming single stop bit mode is selected.
46.5.4.3.1 Eight-bit format with parity disabled
The most significant bit can be used for address mark wakeup.
START
BIT
START
BIT
46.5.4.3.2 Eight-bit format with parity enabled
START
BIT
Figure 46-79. Seven bits of data with LSB first and parity
START
BIT
Figure 46-80. Seven bits of data with MSB first and parity
46.5.4.3.3 Nine-bit format with parity disabled
The most significant bit can be used for address mark wakeup.
START
BIT 0
BIT
ADDRESS
MARK
START
BIT 8
BIT
Freescale Semiconductor, Inc.
Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI
BIT 0 BIT 1 BIT 2 BIT 3
Figure 46-77. Eight bits of data with LSB first
ADDRESS
MARK
BIT 7 BIT 6 BIT 5 BIT 4
Figure 46-78. Eight bits of data with MSB first
BIT 0 BIT 1 BIT 2 BIT 3
BIT 6 BIT 5 BIT 4 BIT 3
BIT 1 BIT 2 BIT 3 BIT 4
Figure 46-81. Nine bits of data with LSB first
BIT 7 BIT 6 BIT 5 BIT 4
Figure 46-82. Nine bits of data with MSB first
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
ADDRESS
MARK
BIT 7 STOP
BIT 4 BIT 5 BIT 6
BIT 0 STOP
BIT 3 BIT 2 BIT 1
STOP
PARITY
BIT 4 BIT 5 BIT 6
STOP
PARITY
BIT 2 BIT 1 BIT 0
ADDRESS
MARK
BIT 8 STOP
BIT 5 BIT 6 BIT 7
BIT 0 STOP
BIT 3 BIT 2 BIT 1
START
BIT
BIT
START
BIT
BIT
START
BIT
BIT
START
BIT
BIT
START
BIT
BIT
START
BIT
BIT
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