Pin Control - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

Address: Base address + C8h offset

This field is reserved.

This read-only field is reserved and always has the value 0.

Filter Length

The digital filter configuration is valid in all digital pin muxing modes. Configures the maximum size of the

glitches, in clock cycles, that the digital filter absorbs for the enabled digital filters. Glitches that are longer

than this register setting will pass through the digital filter, and glitches that are equal to or less than this

12.6 Functional description

12.6.1 Pin control

Each port pin has a corresponding Pin Control register, PORT_PCRn, associated with it.

The upper half of the Pin Control register configures the pin's capability to either

interrupt the CPU or request a DMA transfer, on a rising/falling edge or both edges as

well as a logic level occurring on the port pin. It also includes a flag to indicate that an

interrupt has occurred. The LK bit (bit 15 of Pin Control Register PCRn) locks the lower

16-bits of each Pin Control register and blocks any writes to that register until the next

system reset.

The lower half of the Pin Control register configures the following functions for each pin

within the 32-bit port.

• Pullup or pulldown enable

• Drive strength and slew rate configuration

• Open drain enable

• Passive input filter enable

• Pin Muxing mode

The functions apply across all digital pin muxing modes and individual peripherals do not

override the configuration in the Pin Control register. For example, if an I

enabled on a pin, that does not override the pullup or open drain configuration for that

PORTx_DFWR field descriptions

KV4x Reference Manual, Rev. 2, 02/2015

C function is

Freescale Semiconductor, Inc.