Sout-Serial Output - NXP Semiconductors freescale KV4 Series Reference Manual

Memory Map/Register Definition
Serial Data Out output buffers are controlled through SIU (or
SIUL) and cannot be controlled through the module.
44.3.7 SOUT—Serial Output
Master mode: Serial Output (O)—Transmits serial data.
Slave mode: Serial Output (O)—Transmits serial data.
Serial Data Out output buffers are controlled through SIU (or
SIUL) and cannot be controlled through the module.
44.4 Memory Map/Register Definition
Register accesses to memory addresses that are reserved or undefined result in a transfer
error. Write access to the POPR and RXFRn also results in a transfer error.
Absolute
address
(hex)
4002_C000 Module Configuration Register (SPI_MCR)
4002_C008 Transfer Count Register (SPI_TCR)
Clock and Transfer Attributes Register (In Master Mode)
4002_C00C
(SPI_CTAR0)
Clock and Transfer Attributes Register (In Slave Mode)
4002_C00C
(SPI_CTAR0_SLAVE)
Clock and Transfer Attributes Register (In Master Mode)
4002_C010
(SPI_CTAR1)
4002_C02C Status Register (SPI_SR)
DMA/Interrupt Request Select and Enable Register
4002_C030
(SPI_RSER)
4002_C034 PUSH TX FIFO Register In Master Mode (SPI_PUSHR)
PUSH TX FIFO Register In Slave Mode
4002_C034
(SPI_PUSHR_SLAVE)
4002_C038 POP RX FIFO Register (SPI_POPR)
4002_C03C Transmit FIFO Registers (SPI_TXFR0)
4002_C040 Transmit FIFO Registers (SPI_TXFR1)
1178
NOTE
NOTE
SPI memory map
Register name
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Width
Access Reset value
(in bits)
32 R/W 0000_4001h
32 R/W 0000_0000h
32 R/W 7800_0000h
32 R/W 7800_0000h
32 R/W 7800_0000h
32 R/W 0200_0000h
32 R/W 0000_0000h
32 R/W 0000_0000h
32 R/W 0000_0000h
32 R 0000_0000h
32 R 0000_0000h
32 R 0000_0000h
Freescale Semiconductor, Inc.
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