Tx Fifo Size; Rx Fifo Size; Number Of Pcs Signals; Spi Operation In Low Power Modes - NXP Semiconductors freescale KV4 Series Reference Manual

Chip-specific SPI information
In master mode, the CTAR registers define combinations of transfer attributes, such as
frame size, clock phase, clock polarity, data bit ordering, baud rate, and various delays. In
slave mode only CTAR0 is used, and a subset of its bitfields sets the slave transfer
attributes.

44.1.5 TX FIFO size

SPI Module

44.1.6 RX FIFO Size

SPI supports up to 16-bit frame size during reception.
SPI Module

44.1.7 Number of PCS signals

The following table shows the number of peripheral chip select signals available per SPI
module.
SPI Module

44.1.8 SPI Operation in Low Power Modes

In VLPR and VLPW modes the SPI is functional; however, the reduced system
frequency also reduces the max frequency of operation for the SPI. In VLPR and VLPW
modes the max SPI_CLK frequency is 2MHz.
In stop and VLPS modes, the clocks to the SPI module are disabled. The module is not
functional, but it is powered so that it retains state.
1170
Table 44-1. SPI transmit FIFO size
SPI0
Table 44-2. SPI receive FIFO size
SPI0
Table 44-3. SPI PCS signals
SPI0
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Transmit FIFO size
4
Receive FIFO size
4
PCS Signals
SPI_PCS[5:0]
Freescale Semiconductor, Inc.