External Signal Description; Memory Map/Register Definition; Dmamux Memory Map - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

In this mode, the DMA channel is disabled. Because disabling and enabling of DMA

channels is done primarily via the DMA configuration registers, this mode is used

mainly as the reset state for a DMA channel in the DMA channel MUX. It may also

be used to temporarily suspend a DMA channel while reconfiguration of the system

takes place, for example, changing the period of a DMA trigger.

• Normal mode

In this mode, a DMA source is routed directly to the specified DMA channel. The

operation of the DMAMUX in this mode is completely transparent to the system.

• Periodic Trigger mode

In this mode, a DMA source may only request a DMA transfer, such as when a

transmit buffer becomes empty or a receive buffer becomes full, periodically.

Configuration of the period is done in the registers of the periodic interrupt timer

(PIT). This mode is available only for channels 0–1.

22.3 External signal description

The DMAMUX has no external pins.

This section provides a detailed description of all memory-mapped registers in the

Channel Configuration register (DMAMUX_CHCFG3)

Channel Configuration register (DMAMUX_CHCFG2)

Channel Configuration register (DMAMUX_CHCFG1)

Channel Configuration register (DMAMUX_CHCFG0)

Channel Configuration register (DMAMUX_CHCFG7)

Channel Configuration register (DMAMUX_CHCFG6)

Channel Configuration register (DMAMUX_CHCFG5)

Channel Configuration register (DMAMUX_CHCFG4)

Channel Configuration register (DMAMUX_CHCFG11)

Freescale Semiconductor, Inc.

Chapter 22 Direct memory access multiplexer (DMAMUX)

Table continues on the next page...

KV4x Reference Manual, Rev. 2, 02/2015