Digital Filter - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

• Interrupt disabled, default out of reset

• Active high level sensitive interrupt

• Active low level sensitive interrupt

• Rising edge sensitive interrupt

• Falling edge sensitive interrupt

• Rising and falling edge sensitive interrupt

• Rising edge sensitive DMA request

• Falling edge sensitive DMA request

• Rising and falling edge sensitive DMA request

The interrupt status flag is set when the configured edge or level is detected on the pin or

at the output of the digital input filter, if the digital input digital filter is enabled. When

not in Stop mode, the input is first synchronized to the bus clock to detect the configured

level or edge transition.

The PORT module generates a single interrupt that asserts when the interrupt status flag

is set for any enabled interrupt for that port. The interrupt negates after the interrupt status

flags for all enabled interrupts have been cleared by writing a logic 1 to the ISF flag in

either the PORT_ISFR or PORT_PCRn registers.

The PORT module generates a single DMA request that asserts when the interrupt status

flag is set for any enabled DMA request in that port. The DMA request negates after the

DMA transfer is completed, because that clears the interrupt status flags for all enabled

DMA requests.

During Stop mode, the interrupt status flag for any enabled interrupt is asynchronously

set if the required level or edge is detected. This also generates an asynchronous wake-up

signal to exit the Low-Power mode.

12.6.4 Digital filter

The digital filter capabilities of the PORT module are available in all digital Pin Muxing

modes if the PORT module is enabled.

The clock used for all digital filters within one port can be configured between the bus

clock or the LPO clock. This selection must be changed only when all digital filters for

that port are disabled. If the digital filters for a port are configured to use the bus clock,

then the digital filters are bypassed for the duration of Stop mode. While the digital filters

are bypassed, the output of each digital filter always equals the input pin, but the internal

state of the digital filters remains static and does not update due to any change on the

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.