Transmitting Break Characters - NXP Semiconductors freescale KV4 Series Reference Manual

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Hardware supports odd or even parity. When parity is enabled, the bit immediately

preceding the stop bit is the parity bit.

When the transmit shift register is not transmitting a frame, the transmit data output

signal goes to the idle condition, logic 1. If at any time software clears C2[TE], the

transmitter enable signal goes low and the transmit signal goes idle.

If the software clears C2[TE] while a transmission is in progress, the character in the

transmit shift register continues to shift out, provided S1[TC] was cleared during the data

write sequence. To clear S1[TC], the S1 register must be read followed by a write to D

If S1[TC] is cleared during character transmission and C2[TE] is cleared, the

transmission enable signal is deasserted at the completion of the current frame. Following

this, the transmit data out signal enters the idle state even if there is data pending in the

UART transmit data buffer. To ensure that all the data written in the FIFO is transmitted

on the link before clearing C2[TE], wait for S1[TC] to set. Alternatively, the same can be

achieved by setting TWFIFO[TXWATER] to 0x0 and waiting for S1[TDRE] to set.

46.5.1.4 Transmitting break characters

Setting C2[SBK] loads the transmit shift register with a break character. A break

character contains all logic 0s and has no start, stop, or parity bit. Break character length

depends on C1[M], C1[PE], S2[BRK13], BDH[SBNS] and C4[M10]. See the following

Table 46-70. Transmit break character length

Freescale Semiconductor, Inc.

Chapter 46 Universal Asynchronous Receiver/Transmitter (UART) / FlexSCI

KV4x Reference Manual, Rev. 2, 02/2015

Bits transmitted