Low-Power Bit Usage; Mcg Internal Reference Clocks; Mcg Internal Reference Clock - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Functional description

range within three clocks of the selected DCO clock. After switching to the new DCO

(indicated by the updated C4[DRST_DRS] read bits), the FLL remains unlocked for

several reference cycles. The FLL lock time is provided in the device data sheet as

30.4.2 Low-power bit usage

C2[LP] is provided to allow the FLL or PLL to be disabled and thus conserve power

when these systems are not being used. C4[DRST_DRS] can not be written while C2[LP]

is 1. However, in some applications, it may be desirable to enable the FLL or PLL and

allow it to lock for maximum accuracy before switching to an engaged mode. Do this by

writing 0 to C2[LP].

This module supports two internal reference clocks with nominal frequencies of 32 kHz

(slow IRC) and 4 MHz (fast IRC). The fast IRC frequency can be divided down by

programming of the FCRDIV to produce a frequency range of 32 kHz to 4 MHz.

The MCG Internal Reference Clock (MCGIRCLK) provides a clock source for other on-

chip peripherals and is enabled when C1[IRCLKEN]=1. When enabled, MCGIRCLK is

driven by either the fast internal reference clock (4 MHz IRC which can be divided down

by the FRDIV factors) or the slow internal reference clock (32 kHz IRC). The IRCS

clock frequency can be re-targeted by trimming the period of its IRCS selected internal

reference clock. This can be done by writing a new trim value to the

C3[SCTRIM]:C4[SCFTRIM] bits when the slow IRC clock is selected or by writing a

new trim value to C4[FCTRIM]:C2[FCFTRIM] when the fast IRC clock is selected. The

internal reference clock period is proportional to the trim value written.

C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) and C4[FCTRIM]:C2[FCFTRIM] (if

C2[IRCS]=1) bits affect the MCGOUTCLK frequency if the MCG is in FBI or BLPI

modes. C3[SCTRIM]:C4[SCFTRIM] (if C2[IRCS]=0) bits also affect the

MCGOUTCLK frequency if the MCG is in FEI mode.

Additionally, this clock can be enabled in Stop mode by setting C1[IRCLKEN] and

C1[IREFSTEN], otherwise this clock is disabled in Stop mode.

KV4x Reference Manual, Rev. 2, 02/2015

Freescale Semiconductor, Inc.