Power Modes - NXP Semiconductors freescale KV4 Series Reference Manual

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the bus masters to acknowledge the entry as part of the stop entry sequence. Finally, it

can be used to disable selected bus masters or slaves that should remain inactive during a

If the Flash is not being accessed during WAIT and PSTOP modes, then the Flash Doze

mode can be used to reduce power consumption, at the expense of a slightly longer

wakeup when executing code and vectors from Flash. It can also be used to reduce power

consumption during Compute Operation when executing code and vectors from SRAM.

7.3 Power modes

The power management controller (PMC) provides multiple power options to allow the

user to optimize power consumption for the level of functionality needed.

Depending on the stop requirements of the user application, a variety of stop modes are

available that provide state retention, partial power down or full power down of certain

logic and/or memory. I/O states are held in all modes of operation. The following table

compares the various power modes available.

For each run mode there is a corresponding wait and stop mode. Wait modes are similar

to ARM sleep modes. Stop modes (VLPS, STOP) are similar to ARM sleep deep mode.

The very low power run (VLPR) operating mode can drastically reduce runtime power

when the maximum bus frequency is not required to handle the application needs.

The three primary modes of operation are run, wait and stop. The WFI instruction

invokes both wait and stop modes for the chip. The primary modes are augmented in a

number of ways to provide lower power based on application needs.

Default mode out of reset; on-chip voltage regulator is on.

High Speed run Allows maximum performance of the chip. In this state the chip is able

to operate at a faster frequency compared to normal mode.

Normal Wait -

Allows peripherals to function while the core is in sleep mode, reducing

power. NVIC remains sensitive to interrupts; peripherals continue to be

Normal Stop -

Places chip in static state. Lowest power mode that retains all registers

while maintaining LVD protection. NVIC is disabled; AWIC is used to

wake up from interrupt; peripheral clocks are stopped.

Freescale Semiconductor, Inc.

Table 7-1. Chip power modes

Table continues on the next page...

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 7 Power Management