Flexcan Module Features - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction
The Protocol Engine (PE) submodule manages the serial communication on the CAN
bus:
• Requesting RAM access for receiving and transmitting message frames
• Validating received messages
• Performing error handling
The Controller Host Interface (CHI) sub-module handles message buffer selection for
reception and transmission, taking care of arbitration and ID matching algorithms.
The Bus Interface Unit (BIU) sub-module controls the access to and from the internal
interface bus, in order to establish connection to the CPU and to other blocks. Clocks,
address and data buses, interrupt outputs, DMA and test signals are accessed through the
BIU.

43.2.2 FlexCAN module features

The FlexCAN module includes these distinctive features:
• Full implementation of the CAN protocol specification, Version 2.0 B
• Standard data frames
• Extended data frames
• Zero to eight bytes data length
• Programmable bit rate up to 1 Mb/sec
• Content-related addressing
• Compliant with the ISO 11898-1 standard
• Flexible mailboxes of zero to eight bytes data length
• Each mailbox configurable as receive or transmit, all supporting standard and
extended messages
• Individual Rx Mask registers per mailbox
• Full-featured Rx FIFO with storage capacity for up to six frames and automatic
internal pointer handling with DMA support
• Transmission abort capability
• Flexible message buffers (MBs), totaling 64 message buffers of 8 bytes data length
each, configurable as Rx or Tx
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KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.