Debug Modes Of Operation; Testing The Watchdog - NXP Semiconductors freescale KV4 Series Reference Manual

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25.4.7 Debug modes of operation

You can program the watchdog to disable in debug modes through DBG_EN in the

watchdog control register. This results in the watchdog timer pausing for the duration of

the mode. Register read/writes are still allowed, which means that operations like refresh,

unlock, and so on are allowed. Upon exit from the mode, the timer resumes its operation

from the point of pausing.

The entry of the system into the debug mode does not excuse it from compulsorily

configuring the watchdog in the WCT time after unlock, unless the system bus clock is

gated off, in which case the internal state machine pauses too. Failing to do so still results

in a reset, or interrupt-then-reset, if enabled, to the system. Also, all of the exception

conditions that result in a reset to the system, as described in

Interrupts, are still valid in this mode. So, if an exception condition occurs and the system

bus clock is on, a reset occurs, or interrupt-then-reset, if enabled.

The entry into Debug mode within WCT after reset is treated differently. The WDOG

timer is kept reset to zero and there is no need to unlock and configure it within WCT.

You must not try to refresh or unlock the WDOG in this state or unknown behavior may

result. Upon exit from this mode, the WDOG timer restarts and the WDOG has to be

unlocked and configured within WCT.

25.5 Testing the watchdog

For IEC 60730 and other safety standards, the expectation is that anything that monitors a

safety function must be tested, and this test is required to be fault tolerant. To test the

watchdog, its main timer and its associated compare and reset logic must be tested. To

Table 25-3. Low-power modes of operation

If the WDOG is enabled (WAIT_EN = 1), it can run on bus clock or low-power oscillator clock

(CLK_SRC = x) to generate interrupt (IRQ_RST_EN=1) followed by a reset on time-out. After

reset the WDOG reset counter increments by one.

Where the bus clock is gated, the WDOG can run only on low-power oscillator clock

(CLK_SRC=0) if it is enabled in stop (STOP_EN=1). In this case, the WDOG runs to time-out

twice, and then generates a reset from its backup circuitry. Therefore, if you program the

watchdog to time-out after 100 ms and then enter such a stop mode, the reset will occur after

200 ms. Also, in this case, no interrupt will be generated irrespective of the value of

IRQ_RST_EN bit. After WDOG reset, the WDOG reset counter will also not increment.

The watchdog is

• powered off in VLLSx mode

KV4x Reference Manual, Rev. 2, 02/2015

Generated Resets and

Freescale Semiconductor, Inc.