Message Buffer Structure - NXP Semiconductors freescale KV4 Series Reference Manual

Address: Base address + 880h offset + (4d × i), where i=0d to 15d
Bit 31 30 29 28 27 26 25
R
W
x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x* x*
Reset
* Notes:
• x = Undefined at reset.
Field
MI Individual Mask Bits
Each Individual Mask Bit masks the corresponding bit in both the Mailbox filter and Rx FIFO ID Filter Table
element in distinct ways.
For Mailbox filters, see the RXMGMASK register description.
For Rx FIFO ID Filter Table elements, see the RXFGMASK register description.
0 The corresponding bit in the filter is "don't care."
1 The corresponding bit in the filter is checked.

43.4.53 Message buffer structure

The message buffer structure used by the FlexCAN module is represented in the
following figure. Both Extended (29-bit identifier) and Standard (11-bit identifier) frames
used in the CAN specification (Version 2.0 Part B) are represented. Each individual MB
is formed by 16 bytes.
The memory area from 0x80 to 0x17F is used by the mailboxes.
31 30 29
0x0 EDL BRS ESI
PRIO
0x4
0x8 Data Byte 0
0xC Data Byte 4
CODE - Message Buffer Code
Freescale Semiconductor, Inc.
24 23 22 21 20 19 18 17
CANx_RXIMRn field descriptions
Table 43-105. Message buffer structure
28 27 24 23 22 21
CODE SRR IDE RTR
ID (Standard/Extended)
= Unimplemented or Reserved
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 43 Flex Controller Area Network (FlexCAN)
16 15 14 13 12 11 10 9
MI
Description
20 19 18 17 16 15
DLC
Data Byte 1
Data Byte 5
8 7 6 5 4 3 2 1
8 7 0
TIME STAMP
ID (Extended)
Data Byte 2 Data Byte 3
Data Byte 6 Data Byte 7
0
1121