Compute Operation - NXP Semiconductors freescale KV4 Series Reference Manual

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If the requested DMA transfer cannot cause the DMA request

to negate, then the device remains in a higher power state until

the low power mode is fully exited.

If the DMA request asserts during the Stop mode entry sequence (or reentry if the request

asserts during a DMA wakeup), then an enabled DMA wakeup can cause an aborted

entry into the low power mode, as well as cause the SMC to assert its Stop Abort flag.

An interrupt that occurs during a DMA wakeup causes an immediate exit from the low

power mode (this is optional for Compute Operation) without impacting the DMA

A DMA wakeup can be generated by either a synchronous DMA request or an

asynchronous DMA request. Not all peripherals can generate an asynchronous DMA

request in Stop modes. In general, though, if a peripheral can generate synchronous DMA

requests and also supports asynchronous interrupts in Stop modes, then it can generate an

asynchronous DMA request.

7.2.3 Compute Operation

Compute Operation is an execution or compute-only mode of operation that keeps the

CPU enabled with full access to the SRAM and Flash read port, but places all other bus

masters and bus slaves into their stop mode. Compute Operation can be enabled in either

Run mode or VLP Run mode.

Do not enter any stop mode without first exiting Compute

Because Compute Operation reuses the stop mode logic (including the staged entry with

bus masters disabled before bus slaves), any bus master or bus slave that can remain

functional in stop mode also remains functional in Compute Operation, including

generation of asynchronous interrupts and DMA requests. When enabling Compute

Operation in Run mode, module functionality for bus masters and slaves is the equivalent

of STOP mode. When enabling Compute Operation in VLP Run mode, module

functionality for bus masters and slaves is the equivalent of VLPS mode. The MCG,

PMC, SRAM and Flash read port are not affected by Compute Operation, although the

Flash register interface is disabled.

During Compute Operation, the AIPS peripheral space is disabled and attempted accesses

generate bus errors. The private peripheral space remains accessible during Compute

Operation, including the MCM, NVIC, IOPORT and SysTick. Although access to the

Freescale Semiconductor, Inc.

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 7 Power Management