Memory Map And Registers - NXP Semiconductors freescale KV4 Series Reference Manual

Table of Contents

Advertisement

Memory Map and Registers

37.3.8 EXT_CLK - External Clock Signal
This signal allows a source external to the PWM (typically a timer or an off-chip source)
to control the PWM clocking. In this manner, the PWM can be synchronized to the timer,
or multiple chips can be synchronized to each other.
37.4
Memory Map and Registers
The address of a register is the sum of a base address and an address offset. The base
address is defined at the core level, and the address offset is defined at the module level.
The PWM module has a set of registers for each PWM submodule, for the configuration
logic, and for each fault channel. While the registers are 16-bit wide, they can be
accessed in pairs as 32-bit registers.
Submodule registers are repeated for each PWM submodule. To designate which
submodule they are in, register names are prefixed with SM0, SM1, SM2, and SM3. The
base address of submodule 0 is the same as the base address for the PWM module as a
whole. The base address of submodule 1 is offset $60 from the base address for the PWM
module as a whole. This $60 offset is based on the number of registers in a submodule.
The base address of submodule 2 is equal to the base address of submodule 1 plus this
same $60 offset. The pattern repeats for the base address of submodule 3.
The base address of the configuration registers is equal to the base address of the PWM
module as a whole plus an offset of $180.
The base address of fault channel is equal to the base address of the PWM module as a
whole plus an offset of $18C. Each of the four fields in the fault channel registers
corresponds to fault inputs 3-0.
Absolute
address
(hex)
4003_3000
Counter Register (PWMA_SM0CNT)
4003_3002
Initial Count Register (PWMA_SM0INIT)
4003_3004
Control 2 Register (PWMA_SM0CTRL2)
4003_3006
Control Register (PWMA_SM0CTRL)
4003_300A
Value Register 0 (PWMA_SM0VAL0)
4003_300C Fractional Value Register 1 (PWMA_SM0FRACVAL1)
772
PWMA memory map
Register name
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Width
Access
Reset value
(in bits)
16
R
0000h
16
R/W
0000h
16
R/W
0000h
16
R/W
0400h
16
R/W
0000h
16
R/W
0000h
Freescale Semiconductor, Inc.
Section/
page
37.4.1/780
37.4.2/780
37.4.3/781
37.4.4/783
37.4.5/785
37.4.6/786

Advertisement

Table of Contents
loading

Table of Contents