Crossbar Switch Slave Assignments - NXP Semiconductors freescale KV4 Series Reference Manual

Introduction
20.1.1 Crossbar Switch Master Assignments
The masters connected to the crossbar switch are assigned as follows:
Master module
ARM core code bus
ARM core system bus
DMA

20.1.2 Crossbar Switch Slave Assignments

The slaves connected to the crossbar switch are assigned as follows:
Slave module
Flash memory controller
SRAM controller
AIPS_Lite bus controller/GPIO
20.2 Introduction
The information found here provides information on the layout, configuration, and
programming of the crossbar switch.
The crossbar switch connects bus masters and bus slaves using a crossbar switch
structure. This structure allows up to four bus masters to access different bus slaves
simultaneously, while providing arbitration among the bus masters when they access the
same slave.
20.2.1 Features
The crossbar switch includes these features:
• Symmetric crossbar bus switch implementation
• Allows concurrent accesses from different masters to different slaves
• 32-bit data bus
332
0
1
2
S0
S1
S2
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Master port number
Slave port number
Freescale Semiconductor, Inc.