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Functional description
43.5.10.2 Module Disable mode
This low power mode is normally used to temporarily disable a complete FlexCAN
block, with no power consumption. It is requested by the CPU through the assertion of
the CAN_MCR[MDIS] bit, and the acknowledgement is obtained through the assertion
by the FlexCAN of the CAN_MCR[LPMACK] bit. The CPU must only consider the
FlexCAN in Disable mode when both request and acknowledgement conditions are
satisfied.
If the module is disabled during Freeze mode, it requests to disable the clocks to the PE
and CHI sub-modules, sets the LPMACK bit and negates the FRZACK bit.
If the module is disabled during transmission or reception, FlexCAN does the following:
• Waits to be in either Idle or Bus Off state, or else waits for the third bit of
Intermission and then checks it to be recessive
• Waits for all internal activities like arbitration, matching, move-in and move-out to
finish. A pending move-in is not taken into account.
• Ignores its Rx input pin and drives its Tx pin as recessive
• Shuts down the clocks to the PE and CHI sub-modules
• Sets the NOTRDY and LPMACK bits in CAN_MCR
The Bus Interface Unit continues to operate, enabling the CPU to access memory mapped
registers, except the Rx Mailboxes Global Mask Registers, the Rx Buffer 14 Mask
Register, the Rx Buffer 15 Mask Register, the Rx FIFO Global Mask Register. The Rx
FIFO Information Register, the Message Buffers, the Rx Individual Mask Registers, and
the reserved words within RAM may not be accessed when the module is in Disable
Mode. Exiting from this mode is done by negating the MDIS bit by the CPU, which
causes the FlexCAN to request to resume the clocks and negate the LPMACK bit after
the CAN protocol engine recognizes the negation of disable mode requested by the CPU.
43.5.10.3 Doze mode
This is a system low power mode in which the CPU bus is kept alive and a global Doze
mode request is sent to all peripherals asking them to enter low-power mode. When Doze
mode is globally requested, the DOZE bit in CAN_MCR Register needs to have been
asserted previously for Doze mode to be triggered. The acknowledgement is obtained
through the assertion by the FlexCAN of the LPMACK bit in the same register. The CPU
must only consider the FlexCAN in Doze mode when both request and acknowledgement
conditions are satisfied.
1160
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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