Start Signal; Slave Address Transmission - NXP Semiconductors freescale KV4 Series Reference Manual

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MSB
3
SCL
1
2
SDA
AD7
AD6 AD5
Calling Address
Start
Signal
MSB
SCL
1
2
3
SDA
AD7
AD6
AD5
Calling Address
Start
Signal

45.5.1.1 START signal

The bus is free when no master device is engaging the bus (both SCL and SDA are high).
When the bus is free, a master may initiate communication by sending a START signal.
A START signal is defined as a high-to-low transition of SDA while SCL is high. This
signal denotes the beginning of a new data transfer—each data transfer might contain
several bytes of data—and brings all slaves out of their idle states.

45.5.1.2 Slave address transmission

Immediately after the START signal, the first byte of a data transfer is the slave address
transmitted by the master. This address is a 7-bit calling address followed by an R/W bit.
The R/W bit tells the slave the desired direction of data transfer.
• 1 = Read transfer: The slave transmits data to the master
• 0 = Write transfer: The master transmits data to the slave
Only the slave with a calling address that matches the one transmitted by the master
responds by sending an acknowledge bit. The slave sends the acknowledge bit by pulling
SDA low at the ninth clock.
Freescale Semiconductor, Inc.
LSB
4
5
6
9
7
8
AD4
AD3 AD2 AD1
R/W
Read/
Ack
Bit
Write
LSB
4
5
6
9
7
8
AD4
AD3 AD2 AD1
R/W
XX
Read/
Ack
Bit
Write
Figure 45-14. I2C bus transmission signals
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 45 Inter-Integrated Circuit (I2C)
MSB
3
1
2
4
5
XXX
D7 D6
D5
D4 D3 D2 D1
Data Byte
MSB
1
2
3
4
5
AD7
AD6
AD5
AD4
AD3 AD2 AD1
Repeated
New Calling Address
Start
Signal
LSB
6
9
7
8
D0
No
Stop
Ack
Signal
Bit
LSB
6
9
7
8
R/W
No
Stop
Read/
Ack
Signal
Write
Bit
1247

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