Refresh And Unlock Operations With 8-Bit Access - NXP Semiconductors freescale KV4 Series Reference Manual

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This field is reserved.

This read-only field is reserved and always has the value 0.

3-bit prescaler for the watchdog clock source. A value of zero indicates no division of the input WDOG

clock. The watchdog clock is divided by (PRESCVAL + 1) to provide the prescaled WDOG_CLK.

This field is reserved.

This read-only field is reserved and always has the value 0.

25.9 Watchdog operation with 8-bit access

25.9.1 General guideline

When performing 8-bit accesses to the watchdog's 16-bit registers where the intention is

to access both the bytes of a register, place the two 8-bit accesses one after the other in

25.9.2 Refresh and unlock operations with 8-bit access

One exception condition that generates a reset to the system is the write of any value

other than those required for a legal refresh/update sequence to the respective refresh and

unlock registers.

For an 8-bit access to these registers, writing a correct value requires at least two bus

clock cycles, resulting in an invalid value in the registers for one cycle. Therefore, the

system is reset even if the intention is to write a correct value to the refresh/unlock

Whereas the match for a correct value for a refresh/unlock sequence is as according to the

original definition, the match for an incorrect value is done byte-wise on the refresh/

unlock rather than for the whole 16-bit value. This means that if the high byte of the

refresh/unlock register contains any value other than high bytes of the two values that

make up the sequence, it is treated as an exception condition, leading to a reset or

interrupt-then-reset. The same holds true for the lower byte of the refresh or unlock

to the refresh register, as an example.

Freescale Semiconductor, Inc.

WDOG_PRESC field descriptions

KV4x Reference Manual, Rev. 2, 02/2015

Chapter 25 Watchdog Timer (WDOG)