Speculative Reads - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
As an application example: if both instruction fetches and data references are accessing
flash memory, then control is available to send instruction fetches, data references, or
both to the cache or the single-entry buffer. Likewise, speculation can be enabled or
disabled for either type of access. If both instruction fetches and data references are
cached, then the cache's way resources may be divided in several ways between the
instruction fetches and data references.

31.5.3 Speculative reads

The FMC has a single buffer that reads ahead to the next word in the flash memory if
there is an idle cycle. Speculative prefetching is programmable for each bank for
instruction and/or data accesses using the B0DPE and B0IPE fields of PFB0CR. Because
many code accesses are sequential, using the speculative prefetch buffer improves
performance in most cases.
When speculative reads are enabled, the FMC immediately requests the next sequential
address after a read completes. By requesting the next word immediately, speculative
reads can help to reduce or even eliminate wait states when accessing sequential code
and/or data.
For example, consider the following scenario:
• Assume a system with a 4:1 core-to-flash clock ratio and with speculative reads
enabled.
• The core requests eight sequential longwords in back-to-back requests, meaning
there are no core cycle delays except for stalls waiting for flash memory data to be
returned.
• None of the data is already stored in the cache or speculation buffer.
In this scenario, the sequence of events for accessing the eight longwords is as follows:
1. The first longword read requires 4 to 7 core clocks. See
information.
2. Due to the 128-bit data bus of the flash memory, the second longword read takes
only 1 core clock because the data is already available inside the FMC. For the same
reason, the third and fourth longword reads each take only 1 core clock.
3. Accessing the fifth longword requires 1 core clock cycle. The flash memory read
itself takes 4 clocks, but the access starts immediately after the first read. As a result,
3 clocks for this access overlap with the second, third, and fourth longword reads
from the core.
4. Reading the sixth, seventh, and eighth longwords takes only 1 clock each because the
data is already available inside the FMC.
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KV4x Reference Manual, Rev. 2, 02/2015
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