External Stop Mode; Module Signal Descriptions; Pcs0/Ss-Peripheral Chip Select/Slave Select - NXP Semiconductors freescale KV4 Series Reference Manual

Module signal descriptions

44.2.4.4 External Stop Mode

External Stop mode is used for MCU power management. The module supports the
Peripheral Bus Stop mode mechanism. When a request is made to enter External Stop
mode, it acknowledges the request and completes the transfer that is in progress. When
the module reaches the frame boundary, it signals that the protocol clock to the module
may be shut off.
44.2.4.5 Debug Mode
Debug mode is used for system development and debugging. The MCR[FRZ] bit controls
module behavior in the Debug mode:
• If the bit is set, the module stops all serial transfers, when the MCU is in debug
mode.
• If the bit is cleared, the MCU debug mode has no effect on the module.
44.3 Module signal descriptions
This table describes the signals on the boundary of the module that may connect off chip
(in alphabetical order).
Table 44-4. Module signal descriptions
Signal Master mode
PCS0/SS Peripheral Chip Select 0 (O)
PCS[1:3] Peripheral Chip Selects 1–3
PCS4 Peripheral Chip Select 4
PCS5/ PCSS Peripheral Chip Select 5 /Peripheral
Chip Select Strobe
SCK Serial Clock (O)
SIN Serial Data In
SOUT Serial Data Out
44.3.1 PCS0/SS—Peripheral Chip Select/Slave Select
Master mode: Peripheral Chip Select 0 (O)—Selects an SPI slave to receive data
transmitted from the module.
Slave mode: Slave Select (I)—Selects the module to receive data transmitted from an SPI
master.
1176
Slave mode
Slave Select (I)
(Unused)
(Unused)
Serial Clock (I)
Serial Data In
Serial Data Out
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
I/O
I/O
O
O
O
I/O
I
O
Freescale Semiconductor, Inc.