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Functional description
44.5.2.2 Slave mode
In SPI Slave mode the module responds to transfers initiated by an SPI bus master. It
does not initiate transfers. Certain transfer attributes such as clock polarity, clock phase,
and frame size must be set for successful communication with an SPI master. The SPI
Slave mode transfer attributes are set in the CTAR0. The data is shifted out with MSB
first. Shifting out of LSB is not supported in this mode.
44.5.2.3 FIFO disable operation
The FIFO disable mechanisms allow SPI transfers without using the TX FIFO, CMD
FIFO or RX FIFO. The module operates as a double-buffered simplified SPI when the
FIFOs are disabled. The Transmit and Receive side of the FIFOs are disabled separately.
Setting the MCR[DIS_TXF] bit disables the TX FIFO and CMD FIFO, and setting the
MCR[DIS_RXF] bit disables the RX FIFO.
The FIFO disable mechanisms are transparent to the user and to host software. Transmit
data and commands are written to the PUSHR and received data is read from the POPR.
When the TX FIFO and CMD FIFO are disabled:
• SR[TFFF], SR[TFUF] and SR[TXCTR] behave as if there is a one-entry FIFO
• The contents of TXFRs, SR[TXNXTPTR] are undefined
Similarly, when the RX FIFO is disabled, the RFDF, RFOF, and RXCTR fields in the SR
behave as if there is a one-entry FIFO, but the contents of the RXFR registers and
POPNXTPTR are undefined.
44.5.2.4 Transmit First In First Out (TX FIFO) buffering mechanism
The TX FIFO functions as a buffer of SPI data for transmission. The TX FIFO holds 4
words, each consisting of SPI data. The number of entries in the TX FIFO is device-
specific. SPI data is added to the TX FIFO by writing to the Data Field of module PUSH
FIFO Register (PUSHR). TX FIFO entries can only be removed from the TX FIFO by
being shifted out or by flushing the TX FIFO.
The TX FIFO Counter field (TXCTR) in the module Status Register (SR) indicates the
number of valid entries in the TX FIFO. The TXCTR is updated every time a 8- or 16-bit
write takes place to PUSHR[TXDATA] or SPI data is transferred into the shift register
from the TX FIFO.
1204
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Freescale Semiconductor, Inc.
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