Swoctrl Register Synchronization - NXP Semiconductors freescale KV4 Series Reference Manual

Functional description
update INVCTRL register at
each rising edge of system clock
rising edge
no =
of system
clock ?
= yes
update INVCTRL
with its buffer value
end
Figure 39-220. INVCTRL register synchronization flowchart

39.5.11.9 SWOCTRL register synchronization

The SWOCTRL register synchronization updates the SWOCTRL register with its buffer
value.
984
begin
INVC
0 =
bit ?
INVCTRL is updated
by software trigger
1 =
SWINVC
bit ?
software
0 =
SWSYNC
trigger
bit ?
= 1
update INVCTRL
with its buffer value
end
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
update INVCTRL register by
PWM synchronization
= 1
1 =
SYNCMODE
bit ?
enhanced PWM synchronization
= 0 HWINVC
0 =
bit ?
end
end
hardware
trigger
wait hardware trigger n
= 0
end
INVCTRL is updated
by hardware trigger
= 1
TRIGn
= 0
bit ?
= 1
update INVCTRL
with its buffer value
= 1
HWTRIGMODE
bit ?
= 0
clear TRIGn bit
end
Freescale Semiconductor, Inc.