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Functional description
47.3.6 Port Data Direction Register (GPIOx_PDDR)
The PDDR configures the individual port pins for input or output.
Address: Base address + 14h offset
Bit
31
30
29
28
27
26
25
R
W
0
0
0
0
0
0
0
Reset
Field
PDD
Port Data Direction
Configures individual port pins for input or output.
0
Pin is configured as general-purpose input, for the GPIO function.
1
Pin is configured as general-purpose output, for the GPIO function.
47.4 Functional description
47.4.1 General-purpose input
The logic state of each pin is available via the Port Data Input registers, provided the pin
is configured for a digital function and the corresponding Port Control and Interrupt
module is enabled.
The Port Data Input registers return the synchronized pin state after any enabled digital
filter in the Port Control and Interrupt module. The input pin synchronizers are shared
with the Port Control and Interrupt module, so that if the corresponding Port Control and
Interrupt module is disabled, then synchronizers are also disabled. This reduces power
consumption when a port is not required for general-purpose input functionality.
47.4.2 General-purpose output
The logic state of each pin can be controlled via the port data output registers and port
data direction registers, provided the pin is configured for the GPIO function. The
following table depicts the conditions for a pin to be configured as input/output.
1334
24
23
22
21
20
19
18
17
0
0
0
0
0
0
0
0
GPIOx_PDDR field descriptions
If
Table continues on the next page...
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
16
15
14
13
12
11
10
9
PDD
0
0
0
0
0
0
0
0
Description
8
7
6
5
4
3
2
1
0
0
0
0
0
0
0
0
Then
Freescale Semiconductor, Inc.
0
0
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