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44.5.4.3 Modified SPI Transfer Format (MTFE = 1, CPHA = 0)
In this Modified Transfer Format both the master and the slave sample later in the SCK
period than in Classic SPI mode to allow the logic to tolerate more delays in device pads
and board traces. These delays become a more significant fraction of the SCK period as
the SCK period decreases with increasing baud rates.
The master and the slave place data on the SOUT pins at the assertion of the PCS signal.
After the PCS to SCK delay has elapsed the first SCK edge is generated. The slave
samples the master SOUT signal on every odd numbered SCK edge. The DSPI in the
slave mode when the MTFE bit is set also places new data on the slave SOUT on every
odd numbered clock edge. Regular external slave, configured with CPHA=0 format
drives its SOUT output at every even numbered SCK clock edge.
The DSPI master places its second data bit on the SOUT line one protocol clock after odd
numbered SCK edge if the protocol clock frequency to SCK frequency ratio is higher
than three. If this ratio is below four the master changes SOUT at odd numbered SCK
edge. The point where the master samples the SIN is selected by the
DSPI_MCR[SMPL_PT] field. The master sample point can be delayed by one or two
protocol clock cycles. The SMPL_PT field should be set to 0 if the protocol to SCK
frequency ratio is less than 4. However if this ratio is less than 4, the actual sample point
is delayed by one protocol clock cycle automatically by the design.
The following timing diagrams illustrate the DSPI operation with MTFE=1. Timing
delays shown are:
• T
- PCS to SCK assertion delay
csc
• T
- After SCK PCS negation delay
acs
• T
- master SIN setup time
su_ms
• T
- master SIN hold time
hd_ms
• T
- slave data output valid time, time between slave data output SCK driving
vd_sl
edge and data becomes valid.
• T
- data setup time on slave data input
su_sl
• T
- data hold time on slave data input
hd_sl
• T
- protocol clock period.
sys
The following figure shows the modified transfer format for CPHA = 0 and Fsys/Fsck =
4. Only the condition where CPOL = 0 is illustrated. Solid triangles show the data
sampling clock edges. The two possible slave behavior are shown.
Freescale Semiconductor, Inc.
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 44 Serial Peripheral Interface (SPI)
1213
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