Osc Module States - NXP Semiconductors freescale KV4 Series Reference Manual

29.7.1.2 OSC_DIV (OSC_OSC_DIV)
OSC CLock divider register.
Address: 4006_5000h base + 2h offset = 4006_5002h
Bit 7
Read
ERPS
Write
Reset 0
Field
7–6 ERCLK prescaler. These two bits are used to divide the ERCLK output. The un-divided ERCLK output is
ERPS not affected by these two bits.
00 The divisor ratio is 1.
01 The divisor ratio is 2.
10 The divisor ratio is 4.
11 The divisor ratio is 8.
5 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
4 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
3 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
2 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
1 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
0 This field is reserved.
Reserved This read-only field is reserved and always has the value 0.
29.8 Functional Description
Functional details of the module can be found here.

29.8.1 OSC module states

The states of the OSC module are shown in the following figure. The states and their
transitions between each other are described in this section.
Freescale Semiconductor, Inc.
6 5 4
0 0
0 0 0
OSC_OSC_DIV field descriptions
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
3 2
0 0
0 0
Description
Chapter 29 Oscillator (OSC)
1 0
0 0
0 0
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