Delay Settings - NXP Semiconductors freescale KV4 Series Reference Manual

4096
8192
16384
32768

44.6.5 Delay settings

The following table shows the values for the Delay after Transfer (t
Delay (T ) that can be generated based on the prescaler values and the scaler values set
CSC
in the CTARs. The values calculated assume a 100 MHz protocol frequency.
The clock frequency mentioned above is given as an example in
this chapter. See the clocking chapter for the frequency used to
drive this module in the device.
2
4
8
16
32
64
128
256
512
1024
2048
4096
8192
16384
32768
65536
Freescale Semiconductor, Inc.
Table 44-45. Baud rate values (bps) (continued)
2
12.2k
6.10k
3.05k
1.53k
NOTE
Table 44-46. Delay values
1
20.0 ns
40.0 ns
80.0 ns
160.0 ns
320.0 ns
640.0 ns
1.3 μs
2.6 μs
5.1 μs
10.2 μs
20.5 μs
41.0 μs
81.9 μs
163.8 μs
327.7 μs
655.4 μs
KV4x Reference Manual, Rev. 2, 02/2015
Preliminary
Chapter 44 Serial Peripheral Interface (SPI)
Baud rate divider prescaler values
3
8.14k 4.88k
4.07k 2.44k
2.04k 1.22k
1.02k
DT
3
60.0 ns 100.0 ns
120.0 ns 200.0 ns
240.0 ns 400.0 ns
480.0 ns 800.0 ns
960.0 ns 1.6 μs
1.9 μs 3.2 μs
3.8 μs 6.4 μs
7.7 μs 12.8 μs
15.4 μs 25.6 μs
30.7 μs 51.2 μs
61.4 μs 102.4 μs
122.9 μs 204.8 μs
245.8 μs 409.6 μs
491.5 μs 819.2 μs
983.0 μs 1.6 ms
2.0 ms 3.3 ms
5 7
3.49k
1.74k
872
610 436
) and CS to SCK
Delay prescaler values
5 7
140.0 ns
280.0 ns
560.0 ns
1.1 μs
2.2 μs
4.5 μs
9.0 μs
17.9 μs
35.8 μs
71.7 μs
143.4 μs
286.7 μs
573.4 μs
1.1 ms
2.3 ms
4.6 ms
1227